A team of Rensselaer researchers working to develop 3-D vertical, or stacked, chips into high-speed integrated systems to meet the increasing memory and processing demands that exceed conventional 2-D computer chips as processor speeds increase toward 10 GHz and higher, have received new funding to move the concept to commercialization.

Photo by Russ Kraft

Ronald Gutmann and John McDonald, professors of electrical, computer, and systems engineering (ECSE), and "James" Jian-Qiang Lu, associate research professor of physics and associate professor of ECSE, have long been pioneering interconnect building blocks with a goal to deliver smaller, faster, inexpensive microelectronics and circuits that function in three dimensions. Now, those building blocks are being used in the design of 3-D processor memory stacks, bringing those promises one step closer to reality.

"There is a growing gap between the increased speeds at which microprocessors can operate and the demands for increased memory capacity. 3-D processor memory stacks permit a new arrangement of memory blocks with shortened wire lengths that improve memory speed, allowing 'buses' of information to pass through the channels as opposed to individual bits of information," said McDonald, the lead Rensselaer researcher on processor memory stack design.

According to McDonald, placing the 3-D processor memory stack on top of a computer's microprocessor — the "brain" of the computer where most calculations take place — greatly increases the number of data lines going back and forth between the computer's memory and the processor. This ability to pull multiple lines of data would create a chip more powerful than conventional 2-D chips, and eliminate the memory gap, or "memory wall" as it is often described, said McDonald.

Applications for 3-D integrated circuits include improved weather forecasting equipment and more powerful satellite systems for ground reconnaissance.

The efforts of McDonald, Gutmann, and Lu have attracted the attention of IBM, which recently awarded them a subcontract, funded by the Defense Advanced Research Projects Agency (DARPA) and Space and Naval Warfare Systems Command (SPAWAR), to further explore 3-D integrated circuits with the intent of moving them to market. The specific project involves design of 3-D processor memory stacks, headed by McDonald, and research on key technologies needed for 3-D chip fabrication, such as wafer alignment, headed by Lu. McDonald said that a great deal of research still needs to be done, but the promise of the technology is exciting.

Gutmann and Lu were featured the October 2004 issue of IEEE Computer Magazine in the article “The Lowdown on High-Rise Chips” that explores the engineering of thin interconnects within a high-rise chip.

The 3-D technology research at Rensselaer has been funded for the past five years by the Interconnect Focus Center (IFC): Interconnections for Gigascale, funded by the Microelectronics Research Corporation, DARPA, and New York state. The IFC 3-D program at Rensselaer is led by Gutmann and Lu. Other active participants include Timothy Cale, professor of chemical and biological engineering at Rensselaer, and Peter Persans, professor of physics, applied physics, and astronomy at Rensselaer.

As published in Campus.News, December 6, 2004.

Published December 6, 2004